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FEATURES Low-Noise Amplifiers Provide Low Noise and Low Distortion, Ideal for xDSL Modem Receiver +5 V to 12 V Voltage Supply Low-Power Consumption 4.0 mA/Amp (Typ) Supply Current Voltage Feedback Amplifiers Low Noise and Distortion 2.5 nV/Hz Voltage Noise @ 100 kHz SFDR -95 dBc @ 1 MHz MTPR < -66 dBc High Speed 120 MHz Bandwidth (-3 dB), G = 1 50 V/ s Slew Rate Low-Offset Voltage, 1.5 mV Typical APPLICATIONS ADSL, VDSL, HDSL, and Proprietary xDSL Systems Low-Noise Instrumentation Front End Ultrasound Preamp
Dual High-Speed Low-Noise Op Amps AD8022
FUNCTIONAL BLOCK DIAGRAM
AD8022
- + OUT1 1 -IN1 2 +IN1 3 -VS 4
8 7
+VS OUT2 -IN2 +IN2
- +
6 5
PRODUCT DESCRIPTION
3.0 VOLTAGE NOISE, nV 2.5
The AD8022 consists of two low-noise, high-speed, voltage feedback amplifiers. Both inputs add only 2.5 nV/Hz of voltage noise. These dual amplifiers provide wideband, low-distortion performance, with high-output current optimized for stability when driving capacitive loads. Operating from +5 V to 12 V supplies, the AD8022 typically consumes only 4.0 mA/Amp quiescent current. The AD8022 is available in both an 8-lead microSOIC and an 8-lead SOIC package. Fast overvoltage recovery and wide bandwidth make the AD8022 ideal as the receive channel front end to an ADSL, VDSL or proprietary xDSL transceiver design. Low-noise receive amplifiers in the AD8022 are independent voltage feedback amplifiers and can be configured as the differential receiver from the line transformer or as independent active filters in an xDSL line interface circuit.
pA AND nV/ Hz
2.0
1.5
CURRENT NOISE, pA
1.0
0.5
0 10k
100k FREQUENCY - Hz
1M
Figure 1. Current and Voltage Noise vs. Frequency
REV. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 1999
AD8022-SPECIFICATIONS otherwise noted)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time 0.1% Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Multitone Input Power Ratio1 Conditions
(@ 25 C, VS =
12 V, RL = 500
, G = 1, T MIN = -40 C, TMAX = +85 C, unless
Min Typ 120 25 15 50 30 62 200 Max Unit MHz MHz MHz V/s ns ns ns
VOUT = 0.2 V p-p VOUT = 0.2 V p-p VOUT = 4 V p-p VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p VOUT = 150% of Max Output Voltage, G = 2 VOUT = 2 V p-p fC = 1 MHz fC = 1 MHz G = 7 Differential 26 kHz to 132 kHz 144 kHz to 1.1 MHz f = 100 kHz f = 100 kHz -6 -7.25 -5 -7.5
-95 -100 -67.2 -66 2.5 1.2 -1.5 +2.5 20 0.7 -11.25 to +11.75 +6 +7.25 +5 +7.5
dBc dBc dBc dBc nV/Hz pA/Hz mV mV A A k pF V V mA pF V mA/Amp mA dB C
Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage
TMIN to TMAX Input Bias Current TMIN to TMAX Input Resistance (Differential) Input Capacitance Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Output Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
NOTES 1 Multitone testing performed with 800 mV rms across a 500 load at Points A and B on Figure 17. Specifications subject to change without notice.
Single-Ended RS = 0 , <3 dB of Peaking
-10.1 100 75 +4.5 4.0
+10.1
TMIN to TMAX VS = 5 V to 12 V -40
13.0 5.5 6.1 +85
80
-2-
REV. 0
SPECIFICATIONS otherwise noted)
Parameter DYNAMIC PERFORMANCE -3 dB Small Signal Bandwidth Bandwidth for 0.1 dB Flatness Large Signal Bandwidth Slew Rate Rise and Fall Time Settling Time 0.1% Overdrive Recovery Time NOISE/DISTORTION PERFORMANCE Distortion Second Harmonic Third Harmonic Multitone Input Power Ratio1
(@ 25 C, VS =
2.5 V, RL = 500
, G = 1, TMIN = -40 C, TMAX = +85 C, unless
Min Typ 94 22 10 42 40 75 225 Max
AD8022
Unit MHz MHz MHz V/s ns ns ns
Conditions VOUT = 0.2 V p-p VOUT = 0.2 V p-p VOUT = 3 V p-p VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p, G = 2 VOUT = 2 V p-p VOUT = 150% of Max Output Voltage, G = 2 VOUT = 2 V p-p fC = 1 MHz fC = 1 MHz G = 7 Differential, VS = 6 V 26 kHz to 132 kHz 144 kHz to 1.1 MHz f = 100 kHz f = 100 kHz
-77.5 -94 -69 -66.7 2.3 1 -5.0 -6.25 -5.0 -0.8 +2.0 20 0.7 -1.83 to +2.5 +5.0 +6.25 +5.0 7.5
dBc dBc dBc dBc nV/Hz pA/Hz mV mV A A k pF V V mA pF V mA/Amp mA dB C
Voltage Noise (RTI) Input Current Noise INPUT CHARACTERISTICS RTI Offset Voltage
TMIN to TMAX Input Bias Current TMIN to TMAX Input Resistance (Differential) Input Capacitance Input Common-Mode Voltage Range OUTPUT CHARACTERISTICS Output Voltage Swing Short Circuit Output Current Capacitive Load Drive POWER SUPPLY Operating Range Quiescent Current Power Supply Rejection Ratio OPERATING TEMPERATURE RANGE
NOTES 1Multitone testing performed with 800 mV rms across a 500 load at Points A and B on Figure 17. Specifications subject to change without notice.
Single-Ended RS = 0 , <3 dB of Peaking
-1.38 80 75 +4.5 3.5
+1.48
TMIN to TMAX VS = 1 V -40
13.0 4.25 4.4 +85
86
REV. 0
-3-
AD8022
ABSOLUTE MAXIMUM RATINGS 1 MAXIMUM POWER DISSIPATION
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 V Internal Power Dissipation2 Small Outline Package (R) . . . . . . . . . . . . . . . . . . . . . 1.6 W microSOIC Package (RM) . . . . . . . . . . . . . . . . . . . . . 1.2 W Input Voltage (Common Mode) . . . . . . . . . . . . . . . . . . . . VS Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . 0.8 V Output Short Circuit Duration . . . . . . . . . . . . . . . . . . . . . . Observe Power Derating Curves Storage Temperature Range RM, R . . . . . . -65C to +125C Operating Temperature Range (A Grade) . . . -40C to +85C Lead Temperature Range (Soldering 10 sec) . . . . . . . . . 300C
NOTES 1 Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Specification is for the device in free air: 8-Lead SOIC Package: JA = 160C/W. 8-Lead microSOIC Package: JA = 200C/W.
The maximum power that can be safely dissipated by the AD8022 is limited by the associated rise in junction temperature. The maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150C. Temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. Exceeding a junction temperature of 175C for an extended period can result in device failure. While the AD8022 is internally short circuit protected, this may not be sufficient to guarantee that the maximum junction temperature (150C) is not exceeded under all conditions. To ensure proper operation, it is necessary to observe the maximum power derating curves.
ORDERING GUIDE
Model AD8022AR AD8022ARM AD8022AR-EVAL
Temperature Range -40C to +85C -40C to +85C
Package Description 8-Lead Plastic SOIC 8-Lead microSOIC Evaluation Board
Package Option SO-8 RM-8 SO-8
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD8022 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
2.0 TJ = 150 C
MAXIMUM POWER DISSIPATION - Watts
1.5 8-LEAD SOIC PACKAGE
1.0
8-LEAD MICROSOIC 0.5
0 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 AMBIENT TEMPERATURE - C
80 90
Figure 2. Plot of Maximum Power Dissipation vs. Temperature
-4-
REV. 0
AD8022
5 4 3 2 1 dB dB 0 -1 -2 -3 -4 -5 0.1 1 VIN = 0.4V p-p VIN = 2V p-p VIN = 0.8V p-p 453 + VIN 50 VOUT 56.2 VIN = 0.05V p-p VIN = 0.2V p-p 5 402 4 3 2 1 0 -1 -2 -3 -4 -5 0.1 RF = 0 RF = 402 VIN 50 50 + VOUT 50 RF = 715 RF
10 FREQUENCY - MHz
100
500
1
10 FREQUENCY - MHz
100
500
Figure 3. Frequency Response vs. Signal Level, VS = 12 V, G = 1
Figure 6. Frequency Response vs. R F, G = 1, VS = 12 V, VIN = 22 dBm
0.4 0.3 0.2 0.1 0 dB -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 100k 12V 5.0V 2.5V 1M 10M FREQUENCY - Hz 100M dB G=1 RL = 509V
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 100k 1M 10M FREQUENCY - Hz 12V 5.0V 2.5V 100M G=2 RL = 509V
Figure 4. Fine-Scale Gain Flatness vs. Frequency, G = 1
Figure 7. Fine-Scale Gain Flatness vs. Frequency, G = 2
140 G = +1, RF = 402 120
70 60 NEGATIVE EDGE 50 POSITIVE EDGE 40 30 20
FREQUENCY - MHz
80 60 G = +2, RF = 715
40 20 0
SLEW RATE - V/ s 10 Volts 12 14
100
10 0 2.5
0
2
4 6 8 SUPPLY VOLTAGE -
4.5
6.5 8.5 SUPPLY VOLTAGE - Volts
10.5
12.5
Figure 5. Bandwidth vs. Supply, RL = 500 , V IN = -10 dBm
Figure 8. Slew Rate vs. Supply Voltage, VS = 12 V, G = 2
REV. 0
-5-
AD8022
100mV
100 90
100ns
INPUT
100 90
100mV
100ns
INPUT
10 0%
10
OUTPUT
0%
OUTPUT
100mV
100mV
Figure 9. Noninverting Small Signal Pulse Response, RL = 500 , V S = 12 V, G = 1, R F = 0
Figure 12. Noninverting Small Signal Pulse Response, RL = 500 , V S = 2.5 V, G = 1, RF = 0
2.00V
100 90
100ns
INPUT
100 90
1.00V
100ns
INPUT
10 0%
10
OUTPUT
0%
OUTPUT
2.00V
1.00V
Figure 10. Noninverting Large Signal Pulse Response, RL = 500 , V S = 12 V, G = 1, R F = 0
Figure 13. Noninverting Large Signal Pulse Response, RL = 500 , V S = 2.5 V, G = 1, RF = 0
0.4 0.3 0.2 SETTLING TIME - % SETTLING TIME - % 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.1% +0.1%
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 0 20 40 60 TIME - ns 80 100 120 -0.1% +0.1%
0
20
40
60 TIME - ns
80
100
120
Figure 11. Settling Time to 0.1%, V S = 12 V, Step Size = 2 V p-p, G = 2, RL = 500
Figure 14. Settling Time to 0.1%, VS = 2.5 V, Step Size = 2 V p-p, G = 2, RL = 500
-6-
REV. 0
AD8022
-20 -30 HARMONIC DISTORTION - dBc -20 -40 -50 -60 3RD -70 2ND -80 -90 -100 -120 -120 HARMONIC DISTORTION - dBc 0
-40
-60 2ND -80 3RD
-100
0
5 10 15 OUTPUT VOLTAGE - Volts p-p
20
0
0.5
1.0 1.5 2.0 OUTPUT VOLTAGE - Volts p-p
2.5
3.0
Figure 15. Distortion vs. Output Voltage, VS = 12 V, G = 2, f = 1 MHz, RL = 500 , RF = 715
Figure 18. Distortion vs. Output Voltage, VS = 2.5 V, G = 2, f = 1 MHz, RL = 500 , R F = 715
-50 -60 HARMONIC DISTORTION - dB -70 3RD -80 -90 -100 -110 -120 -130 1k 10k 100k FREQUENCY - Hz 1M 2ND HARMONIC DISTORTION - dB
-50 -60 -70 2ND -80 -90 -100 -110 -120 -130 1k 10k 100k FREQUENCY - Hz 1M 3RD
Figure 16. Distortion vs. Frequency, VS = 12 V, RL = 500 , R F = 715 , V OUT = 2 V p-p, Gain = 1
Figure 19. Distortion vs. Frequency, VS = 2.5 V, RL = 500 , R F = 715 , V OUT = 2 V p-p, Gain = 1
+V
4
1k
3
VIN
1k 1k 500 1k VOUT
AD8022
1/2 VOS - mV
2 1
VS =
2.5V
715 250 715 500
0 -1 -2
VS = 12V
AD8022
1/2 -3 -4 -12.5 -V
-10.0 -7.5
-5.0 -2.5 0 2.5 VCM - Volts
5.0
7.5
10.0
12.5
Figure 17. Multitone Power Ratio Test Circuit
Figure 20. Input Common-Mode Voltage Range
REV. 0
-7-
AD8022
10dB/DIV
-69.0dBc -66.7dBc 10dB/DIV 102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4 FREQUENCY - kHz
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY - kHz
Figure 21. Multitone Power Ratio: V S = 6 V, RL = 500 , Full Rate ADSL (DMT), Downstream
Figure 24. Multitone Power Ratio: VS = 6 V, RL = 500 , Full Rate ADSL (DMT), Upstream
10dB/DIV
-67.2dBc -66.0dBc 10dB/DIV 102.4 103.4 104.4 105.4 106.4 107.4 108.4 109.4 110.4 111.4 112.4 FREQUENCY - kHz
549.3 550.3 551.3 552.3 553.3 554.3 555.3 556.3 557.3 558.3 559.3 FREQUENCY - kHz
Figure 22. Multitone Power Ratio: V S = 12 V, RL = 500 , Full Rate ADSL (DMT), Downstream
Figure 25. Multitone Power Ratio: VS = 12 V, RL = 500 , Full Rate ADSL (DMT), Upstream
4.5 4.0 3.5 BIAS CURRENT - A 3.0 2.5 VS = 2.0 1.5 1.0 0.5 0 -60 2.5V VS = 12V SUPPLY CURRENT - Total mA
8.5 8.0 VS = 7.5 7.0 6.5 VS = 6.0 5.5 5.0 -50 2.5V 12V
-40
-20
0
20 40 60 80 TEMPERATURE - C
100
120
140
0
50 TEMPERATURE - C
100
150
Figure 23. Bias Current vs. Temperature
Figure 26. Total Supply Current Over Temperature
-8-
REV. 0
AD8022
5 100 FREQUENCY RESPONSE - dB 31.6 OUTPUT IMPEDANCE - 10 3.16 1 0.316 0.1 0.0316 4 3 2 1 0 -1 -2 -3 -4 30k 100k 1M 10M FREQUENCY - Hz 100M 500M -5 0.1 0pF 30pF VIN 50 CL 715 715 + RS 453 VOUT 56.2 50pF
1
10 FREQUENCY - kHz
100
500
Figure 27. Output Impedance vs. Frequency, VS = 12 V
Figure 30. Frequency Response vs. Capacitive Load, CL = 0 pF, 30 pF and 50 pF, RS = 0
0 -10 -20 CROSSTALK - dB CROSSTALK - dB -30 -40 -50 -60 SIDE B OUT -70 -80 -90 -100 100k 1M 10M FREQUENCY - Hz 100M SIDE A OUT
0 -10 -20 -30 -40 -50 -60 SIDE B OUT -70 -80 -90 -100 100k 1M 10M FREQUENCY - Hz 100M SIDE A OUT
Figure 28. Output-to-Output Crosstalk vs. Frequency, VS = 12 V
Figure 31. Output -to-Output Crosstalk vs. Frequency, VS = 2.5 V
-10 604 604
0 SIDE A
-30 154 56.7 -50 154
50 VOLTAGE OFFSET - mV
-0.5 SIDE B SIDE A SIDE B -1.5 VS = +12V -2.0 VS = 2.5V
CMRR - dB
-1.0
-70
-90
-110 1k
10k
100k FREQUENCY - Hz
1M
-2.5 -60
-40
-20
0 20 40 60 80 TEMPERATURE - Degrees
100
120
140
Figure 29. CMRR vs. Frequency
Figure 32. Voltage Offset vs. Temperature
REV. 0
-9-
AD8022
0 -10 POWER SUPPLY REJECTION - dB POWER SUPPLY REJECTION - dB -20 -30 -PSRR -40 -50 +PSRR -60 -70 -80 -90 -100 10k 100k 1M FREQUENCY - Hz 10M 100M 0 -10 -20 -PSRR -30 -40 +PSRR -50 -60 -70 -80 -90 -100 10k 100k 1M FREQUENCY - Hz 10M 100M
Figure 33. Power Supply Rejection vs. Frequency, VS = 12 V
THEORY OF OPERATION
Figure 34. Power Supply Rejection vs. Frequency, VS = 2.5 V
APPLICATIONS
The AD8022 is a voltage-feedback op amp designed especially for ADSL or other applications requiring very low voltage and current noise along with low-supply current, low distortion, and ease of use. The AD8022 is fabricated on Analog Devices' proprietary eXtraFast Complementary Bipolar (XFCB) process, which enables the construction of PNP and NPN transistors with similar fTs in the 4 GHz region. The process is dielectrically isolated to eliminate the parasitic and latch-up problems caused by junction isolation. These features enable the construction of high-frequency, lowdistortion amplifiers with low-supply currents.
+VS
15 +IN 15 7.5pF -IN 600 A OUTPUT
The low-noise AD8022 dual xDSL receiver amplifier is specifically designed for the dual differential receiver amplifier function within xDSL transceiver hybrids as well as other low-noise amplifier applications. The AD8022 may be used in receiving modulated signals including Discrete Multitone (DMT) on either end of the subscriber loop. Communication systems designers can be challenged when designing an xDSL modem transceiver hybrid capable of receiving the smallest signals embedded in noise that inherently exists on twisted pair phone lines. Noise sources include Near End Cross Talk (NEXT), Far End Cross Talk (FEXT), background and impulse noise, all of which are fed, to some degree, into the receiver front end. Based on a Bellcore noise survey, the background noise level for typical twisted pair telephone loop is said to be -140 dBm/Hz or 31 nV/Hz. It is therefore important to minimize the noise added by the receiver amplifiers in order to preserve as much Signal-to-Noise Ratio (SNR) as is possible. With careful transceiver hybrid design using the AD8022 dual low-noise receiver amplifier, maintaining power density levels lower than -140 dBm/Hz in ADSL modems is easily achieved.
DMT Modulation and Multitone Power Ratio (MTPR)
-VS OFFSET NULL
Figure 35. Simplified Schematic
As shown in Figure 35, the AD8022 input stage consists of an NPN differential pair in which each transistor operates a 300 A collector current. This gives the input devices a high transconductance and hence gives the AD8022 low-input noise of 2.5 nV/Hz @ 100 kHz. The input stage drives a folded cascode that consists of a pair of PNP transistors. These PNP's then drive a current mirror that provides a differential-input to single-ended-output conversion. The output stage provides a high-current gain of 10,000, so that the AD8022 can maintain a high-dc openloop gain, even into low-load impedances.
ADSL systems rely on Discrete Multitone (or DMT) modulation to carry digital data over phone lines. DMT modulation appears in the frequency domain as power contained in several individual frequency subbands, sometimes referred to as tones or bins, each of which is uniformly separated in frequency. (See Figures 21, 22, 24, and 25 for MTPR results while the AD8022 receives DMT driving 800 mV rms across 500 differential load). A uniquely encoded, Quadrature Amplitude Modulation (QAM) signal occurs at the center frequency of each subband or tone. Difficulties will exist when decoding these subbands if a QAM signal from one subband is corrupted by the QAM signal(s) from other subbands, regardless of whether the corruption comes from an adjacent subband or harmonics of other subbands. Conventional methods of expressing the output signal integrity of line receivers such as spurious free dynamic range (SFDR), single tone harmonic distortion or THD, two-tone Intermodulation Distortion (IMD) and third-order intercept (IP3) become significantly less meaningful when amplifiers are required to
-10-
REV. 0
AD8022
process DMT and other heavily modulated waveforms. A typical xDSL downstream DMT signal may contain as many as 256 carriers (subbands or tones) of QAM signals. MTPR is the relative difference between the measured power in a typical subband (at one tone or carrier) versus the power at another subband specifically selected to contain no QAM data. In other words, a selected subband (or tone) remains open or void of intentional power (without a QAM signal) yielding an empty frequency bin. MTPR, sometimes referred to as the "empty bin test," is typically expressed in dBc, similar to expressing the relative difference between single tone fundamentals and second or third harmonic distortion components. Measurements of MTPR are typically made at the output of the receiver directly across the differential load. Other components aside, the receiver function of an ADSL transceiver hybrid will be affected by the turns ratio of the selected transformers within the hybrid design. Since a transformer reflects the secondary voltage back to the primary side by the inverse of the turns ratio 1/N, increasing the turns ratio on the secondary side reduces the voltage across the primary side inputs of the differential receiver. Increasing the turns ratio of the transformers may inadvertently cause a reduction of the SNR by reducing the received signal strength.
Channel Capacity and SNR Generating DMT
The efficiency of an ADSL system in delivering the digital data embedded in the DMT signals can be compromised when the noise power of the transmission system increases. The graph below shows the relationship between SNR and the relative maximum number of bits per tone or subband while maintaining a bit error rate at 1E-7 errors per second.
60.00
At this time, DMT modulated waveforms are not typically menu selectable items contained within arbitrary waveform generators. AWGs that are available today may not deliver DMT signals sufficient in performance with regard to MTPR due to limitations in the D/A converters and output amplifiers used by AWG manufacturers. Similar to evaluating single tone distortion performance of an amplifier, MTPR evaluation requires a DMT signal generator capable of delivering MTPR performance better than that of the driver under evaluation. Generating DMT signals can be accomplished using a Tektronics AWG 2021 equipped with Opt 4, (12-bit/24-bit, TTL Digital Data Out), digitally coupled to Analog Devices' AD9754, a 14-bit TxDAC, buffered by an AD8002 amplifier configured as a differential driver. See Figure 37 for schematics of a circuit used to generate DMT signals that can achieve down to -80 dBc of MTPR performance, sufficient for use in evaluating xDSL receivers. WFM files are needed to produce the necessary digital data required to drive the TxDAC from the optional TTL Digital Data output of the TEK AWG2021. Copies of .WFM files for upstream and downstream DMT waveforms with a peak-to-average ratio (crest factor) of ~5.3 can be obtained through the Analog Devices web site. http://products.analog.com/products/info.asp? product=AD8022 Upstream data is contained in the ...24.wfm files and downstream data in the ...128.wfm files. These DMT modulated signals are used to evaluate xDSL products for Multitone Power Ratio or MTPR performance. The data files are used in pairs (adslu24.wfm and adsll24.wfm go together, etc.) and are loaded into Tektronics AWG2021 arbitrary waveform generator. The adslu24.wfm is loaded via the TEK AWG2021 floppy drive into Channel 1 while the adsll24.wfm is simultaneously loaded into Channel 2. The number in the file name, prefixed with `u,' goes into CH1 or upper channel and the `l' goes into CH2 or the lower channel. Twelve bits from channel CH1 are combined with two bits from CH2 to achieve 14-bit digital data at the digital outputs of the TEK 2021. The resulting waveforms produced at the AD9754-EB outputs are then buffered and amplified by the AD8002 differential driver to achieve 14-bit performance from this DMT signal source.
Power Supply and Decoupling
50.00
40.00 SNR - dB
30.00
20.00
10.00
0.00 0 5 BITS/TONE 10 15
Figure 36. ADSL DMT SNR vs. Bits/Tone
The AD8022 should be powered with a good quality (i.e., low noise) dual supply of 12 V for the best overall performance. The AD8022 circuit will also function at voltages lower than 12 V. Careful attention must be paid to decoupling the power supply pins. A pair of 10 F capacitors located in near proximity to the AD8022 is required to provide good decoupling for lower frequency signals. In addition, 0.1 F decoupling capacitors should be located as close to each of the power supply pins as is physically possible.
REV. 0
-11-
DVDD B3 TP4 TP18 TP5 C4 10 F
A A A
DGND B4 TP19 TP6 TP7 B5 B6
AVDD
AGND
AVEE
AVCC
AD8022
B1
B2
TP3
TP2
J1 A EXTCLK 1 2 3 R15 49.9 B
C3 10 F DVDD R5 R3 16 PINDIP RES PK 1 2 3 4 5 6 7 8 9 10 2 3 4 5 6 7 8 9 10 1 U1 AVDD C7 1F C8 0.1 F
A
C5 10 F DVDD R7 TP8 C9 0.1 F
C6 10 F
TP1
CLK JP1
R1 1 2 3 4 5 6 7 8 9 10
1
P1
2 3 4 5 6 7 8 9 10
AD9754
AVDD OUT 1 OUT 2
C19 C1 C2 C25 C26 C27 C28 C29
1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
16 PINDIP RES PK
1 2 3 4 5 6 7 8 9 10 11 12 13 14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 CLOCK DVDD DCOM NC AVDD COMP2 IOUTA IOUTB ACOM COMP1 FS ADJ REFIO REFLO SLEEP TP11
A
28 27 26 25 24 23 22 21 20 19 18 17 16 15
TP13 TP10 AVDD R16 2k R 20k TP9
CT1
A
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 C30 C31 C32 C33 C34 C35 C36 1 2 3 4 5 6 7 10 9 8 7 6 5 4 3 2 1 R6 R8 DVDD DVDD R4 1 1
A A A
1 3 5 7 9 11 13 TO TEK 15 AWG 17 2021 19 21 23 25 27 29 31 33 35 37 39 16 15 14 13 12 11 10 10 9 8 7 6 5 4 3 2 1 2 PDIN J2 TP12 JP2 3 C11 0.1 F
Figure 37. DMT Signal Generator Schematic
10 9 8 7 6 5 4 3 2 R17 49.9 AVCC 0.1 F 1F
A
-12-
10k
A
TP14 JP4
C10 0.1 F
10 9 8 7 6 5 4 3 2
1
R2
AVDD
J3 249
OUT1
C12 22pF
49.9 750 226 750
A
AD8002
A
A
DIFFERENTIAL DMT OUTPUTS
J4 1F 0.1 F 10k
A A
OUT2
AD8002
249
C13 22pF AVEE
49.9
A
A
A
REV. 0
AD8022
EVALUATION BOARDS Layout Considerations
The evaluation board layout of Figures 40, 41, and 42 is our standard dual SOIC noninverting evaluation circuit offering the ability to evaluate the AD8022 in typical op amp circuits, is available from Analog Devices Inc. In addition, the AD8022 receiver function may be added to on our ADSL EVAL boards. The AD8016ARB-EVAL, the AD8016ARP-EVAL, the AD8017AR-EVAL and AD8018ARU-EVAL boards are available through Analog Devices. These platforms provide the capability to fully evaluate the Analog Devices ADSL transceiver hybrid. All of the ADSL evaluation boards mentioned above can accommodate the evaluation of the AD8022 as a receiver amplifier when installed in the U2 location. The receiver circuit on these boards is typically unpopulated. Requesting samples of the AD8022 along with the EVAL board of your choice will provide the capability to evaluate the AD8022 along with many other Analog Devices ADSL line driver products in a typical transceiver circuit. The evaluation circuits have been designed to replicate the CPE or CO side analog transceiver hybrid circuits. The ADSL EVAL circuits mentioned above are designed using a two transformer transceiver topology, including a line receiver, line driver, line matching network, an RJ11 jack for interfacing to line simulators, and transformer-coupled inputs for single-todifferential input conversion.
680pF 5% NPO 12V 3 2 8 AD8022 1 U27
As is the case with all "hi speed" amplifiers, careful attention to printed circuit board layout details will prevent associated board parasitics from becoming problematic. Proper RF design technique is mandatory. The PCB should have a ground plane covering all unused portions of the component side of the board to provide a low-impedance return path. Removing the ground plane from the area near the input signal lines will reduce stray capacitance. Chip capacitors should be used for the supply bypassing. One end of the capacitor connected to the ground plane and the other no more than 1/8 inch away from each supply pin. An additional large (0.47 F to 10 F) tantalum capacitor should be connected in parallel, although not necessarily as close, in order to supply current for fast, large signal changes at the AD8022 output. Signal lines connecting the feedback and gain resistors should be as short as possible, minimizing the inductance and stray capacitance associated with these traces. Locate termination resistors and loads as close as possible to the input(s) and output respectively. Adhere to stripline design techniques for long signal traces (greater than about 1 inch). Following these generic guidelines will improve the performance of the AD8022 in all applications.
7.5 2.5 -2.5 -7.5 -12.5 dB
1.91k 1%
2.43k 1%
-17.5 -22.5 -27.5 -32.5
820pF 10% 6V 1.69k 1% 0.1 F 50V 5% NPO 820pF 10%
1k
1% -37.5 -42.5 -47.5 10k 100k 1M FREQUENCY - Hz 10M
0.1 F 16V 10% X7R
1k 6 5 U27 7
1%
Figure 39. Frequency Response of Sallen-Key Filter
4 AD8022
1.91k 1%
2.43k 1%
680pF 5% NPO
Figure 38. Differential Input Sallen-Key Filter Using AD8022 on Single Supply, 12 V
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AD8022
Figure 40.
Figure 41.
Figure 42.
RF 715 +VS RG 715 J1 RT 49.9 RC 0 -VS AMP #1 +VS C3 0.01 F C4 0.01 F -VS C1 10 F C2 10 F BYPASSING G=2 RO 0 J2 J3 49.9 RG 715
RF 715 G=2 RO 0 J4 RC 0 AMP #2
AD8022
AD8022
499
499
Figure 43. Evaluation Board Schematic
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AD8022
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
8-Lead Plastic SOIC (SO-8)
0.1968 (5.00) 0.1890 (4.80)
8 5 4
8-Lead microSOIC (RM-8)
C3714-8-10/99
0.120 (3.05) 0.112 (2.84) 0.043 (1.09) 0.037 (0.94) 0.011 (0.28) 0.003 (0.08) 33 27 0.028 (0.71) 0.016 (0.41) 0.122 (3.10) 0.114 (2.90)
0.1574 (4.00) 0.1497 (3.80) PIN 1
1
0.2440 (6.20) 0.2284 (5.80)
8
5
0.122 (3.10) 0.114 (2.90)
1 4
0.199 (5.05) 0.187 (4.75)
0.0500 (1.27) BSC 0.0098 (0.25) 0.0040 (0.10) SEATING PLANE 0.0688 (1.75) 0.0532 (1.35) 0.0192 (0.49) 0.0138 (0.35) 8 0.0098 (0.25) 0 0.0075 (0.19)
0.0196 (0.50) 0.0099 (0.25)
45
PIN 1 0.0256 (0.65) BSC 0.120 (3.05) 0.112 (2.84) 0.006 (0.15) 0.002 (0.05) 0.018 (0.46) SEATING 0.008 (0.20) PLANE
0.0500 (1.27) 0.0160 (0.41)
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PRINTED IN U.S.A.

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